Computing devices rely on memory or storage devices to store data and commands that enable the computing devices to perform their functions. Currently many computing systems use multiple different types of memory devices, due to the performance and characteristics of the different memory devices. There has been research into providing a universal memory that can fill the different roles of the traditional different memory types. Magnetic-based memory (MRAM (magnetoresistive random access memory)) devices have many characteristics that are desired for a universal memory.
Traditionally a computing device might use DRAM (dynamic random access memory), SRAM (static random access memory), and Flash in the same device for different applications. SRAM is typically very fast and is traditionally favored for processor cache applications. DRAM provides very high density and is traditionally favored for main system memory. However, both SRAM and DRAM are volatile, meaning their state becomes non-deterministic in the event power is interrupted to the device. Flash is nonvolatile, and so will maintain deterministic state in the event of interruption of power, but is much slower than SRAM or DRAM. Additionally, flash degrades over time due to the write mechanism, and thus has a limited number of write cycles. SRAM does not provide the density available with DRAM, and tends to use more power than DRAM, even though DRAM requires regular refreshing.
Magnetic memory has been shown to have similar access speeds traditionally associated with SRAM, and provides densities traditionally associated with DRAM. Magnetic memory uses much less power than DRAM or SRAM. Additionally, magnetic memory can be nonvolatile such as flash, but does not suffer the same degradation. However, there are many issues with magnetic memory. One significant challenge with magnetic memory is its write energy and write time. Writing to a magnetic memory can be asymmetrical, where writing to one state is much more costly than writing to the other. For example, in STT (spin transfer torque) memory devices (e.g., STTRAM), writing to an AP (anti-parallel) state takes an order of magnitude longer than writing to a P (parallel) state.
Traditional approaches to the asymmetrical write performance of STTRAM fall under one of the two categories: 1) Trading off persistence to improve write performance; and, 2) Early termination. With persistence trade, a system uses a low-retention time design with less reliable cells to have better write performance. However, such an approach can significantly impair the usefulness of STTRAM. With early termination, a system can detect when a cell is switched and terminate the write operations per cell to prevent unnecessary current flowing through the magnetic terminal junction (MTJ). However, early termination does not improve worst case write performance, which means it has no effect on overall write latency, seeing that a system has to plan for worst case latency to ensure deterministic operation.
Descriptions of certain details and implementations follow, including a description of the figures, which may depict some or all of the embodiments described below, as well as discussing other potential embodiments or implementations of the inventive concepts presented herein.